Multiplexing latch circuit and method

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11296703
APP PUB NO 20200153435A1
SERIAL NO

16745102

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Abstract

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A multiplexing latch circuit includes first, second, and third tristate inverters and an inverter. The first tristate inverter includes an output terminal and an input terminal coupled to a first data line, the second tristate inverter includes an output terminal and an input terminal coupled to a second data line, and the third tristate inverter includes an input terminal and an output terminal. The first inverter includes an input terminal coupled to the output terminals of each of the first, second, and third tristate inverters, an output terminal coupled to the input terminal of the third tristate inverter, and is configured to generate an output signal based on data received on one of the first data line or the second data line.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hong, Hyunsung Kanata, CA 19 29

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