Wide bit memory using post passivation interconnection scheme
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United States of America Patent
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Jun 4, 2002
Grant Date -
N/A
app pub date -
Mar 7, 2001
filing date -
Mar 7, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention relates to a wide-bit memory output structure that comprises a chip having a plurality of output driver circuit cells. Each of the output driver circuit cells includes a power node, a ground node, and a signal node that are connected to respectively a first power line, a first ground line, and a first signal line. An extremity of each first power, ground, and signal line is exposed on the chip. The chip is provided with a thick metal structure thereupon, which comprises a wide power bus and a wide ground bus that are connected to respectively a plurality of second power lines and a plurality of second ground lines. Finally, the first and second power lines, first and second ground lines, and first and second signal lines are respectively connected to one another. An extremity of respectively the wide power bus, the ground bus and the second signal lines is equally exposed externally from the thick metal structure.
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