Enhanced timing margin memory interface
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United States of America Patent
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Dec 25, 2007
Grant Date -
Mar 2, 2006
app pub date -
Aug 17, 2005
filing date -
Aug 30, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.
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