Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same
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United States of America Patent
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Dec 5, 2006
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app pub date -
Sep 24, 2004
filing date -
Sep 24, 2004
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Abstract
A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses and substantially planar step surfaces, and implanting a dopant species through the mask layer into a portion of the semiconductor layer adjacent to the termination of the pn junction. The semiconductor layer is annealed to activate at least a portion of the implanted dopant species to form the graded junction termination extension.
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