Pipelined multiplier for signed multiplication
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 4, 1995
Grant Date -
N/A
app pub date -
Nov 9, 1993
filing date -
Nov 9, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A pipelined multiplier for signed multiplication has a plurality of pipeline stages, each of which includes a row of registers, and a row of operating cells. The operating cells includes a plurality: of AND gates, NAND gates, half adders, and full adders connected to perform the signed multiplication according to the Hatamian-Cash algorithm. The pipelined multiplier is characterized by that the most significant bit of the product is directly obtained from the previous less significant bit of the product.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully