Array of nanoscopic MOSFET transistors and fabrication methods
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United States of America Patent
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Mar 8, 2011
Grant Date -
Oct 6, 2005
app pub date -
May 10, 2005
filing date -
Jul 15, 2003
priority date (Note) -
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Abstract
A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.
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