Semiconductor memory
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United States of America Patent
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Oct 31, 1995
Grant Date -
N/A
app pub date -
Dec 28, 1994
filing date -
Dec 28, 1993
priority date (Note) -
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Abstract
There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.
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