Single-stage and multi-stage low power interconnect architectures

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United States of America Patent

PATENT NO 7190286
SERIAL NO

11314236

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Abstract

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An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caputa, Peter Linkoping, SE 6 24
De, Vivek K Beaverton, OR 212 4524
Ghoneima, Maged M Evanston, IL 3 6
Ismail, Yehea I Evanston, IL 4 47
Khellah, Muhammad M Lake Oswego, OR 114 1799
Krishnamurthy, Ram Portland, OR 125 1104
Tschanz, James W Portland, OR 93 1154
Ye, Yiben Hillsboro, OR 2 4

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