Write response signalling within a communication bus
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United States of America Patent
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May 1, 2007
Grant Date -
Dec 8, 2005
app pub date -
Jun 8, 2004
filing date -
Jun 8, 2004
priority date (Note) -
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Abstract
An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read address channel. The provision of a dedicated write response channel frees the read data channel to be more efficiently used for the transfer of read data. Transactions may be burst mode transactions with a single write response corresponding to the write transaction as a whole.
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