Decoder circuit with short channel depletion transistors
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United States of America Patent
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-
Sep 28, 1999
Grant Date -
N/A
app pub date -
Aug 26, 1996
filing date -
Aug 26, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.
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- Non-US Classification not provided for expired patents
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