Multi-trapping layer flash memory cell

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United States of America Patent

PATENT NO 8816422
APP PUB NO 20080067577A1
SERIAL NO

11521805

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Abstract

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A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ong, Tong-Chern Taipei, TW 39 434
Wang, Ming-Tsong Taipei, TW 26 219

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