Method and apparatus for disabling a clock signal within a multithreaded processor
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United States of America Patent
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Apr 19, 2005
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N/A
app pub date -
Mar 8, 2002
filing date -
Dec 9, 1999
priority date (Note) -
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Abstract
A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.
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