Memory with 6T small aspect ratio cells having metal.sub.--1 elements physically connected to metal.sub.--0 elements
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United States of America Patent
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Aug 8, 2006
Grant Date -
N/A
app pub date -
Aug 2, 2001
filing date -
Aug 9, 2000
priority date (Note) -
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Abstract
A method of forming a memory circuit comprising six transistor memory cells. The memory cells comprise first and second inverters. The inverters comprise respective first and second drive transistors and first and second pull-up transistors. The method also forms a plurality of conducting plugs. A first conducting plug is coupled to the first inverter and a second conducting plug is coupled to the first pull-up transistor and to the gates of the second drive transistor and the second pull-up transistor. A third conducting plug is coupled to the second inverter and a fourth conducting plug coupled to the second pull-up transistor and to the gates of the first drive transistor and the first pull-up transistor. The method also forms conducting elements. A first conducting element contacts the first conducting plug and the second conducting plug and a second conducting element contacts the third conducting plug and the fourth conducting plug.
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