Method and apparatus for laying out cells in a semiconductor device
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United States of America Patent
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Feb 27, 2007
Grant Date -
Oct 5, 2006
app pub date -
Jun 21, 2005
filing date -
Mar 30, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for generating layout data for macro cells in a core region of a semiconductor device. The method includes generating wiring margin-added macro cells, calculating the area of a maximum standard cell region by excluding the area of the wiring margin-added macro cells from the area of the core region, calculating the area of an actual standard cell region in which layout of standard cells is enabled in the core region in accordance with a floor plan laying out the wiring margin-added macro cells, calculating a dead space percentage of the floor plan from the area of the maximum standard cell region and the area of the actual standard cell region, and correcting the floor plan by moving at least one wiring margin-added macro cells so that the dead space percentage becomes less than a reference value.
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