System and method for testing integrated circuits
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United States of America Patent
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Jul 10, 2007
Grant Date -
Nov 17, 2005
app pub date -
May 3, 2004
filing date -
May 3, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A module (236, 236') containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).
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