Row address latching for multiple activate command protocol

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11972123
APP PUB NO 20240069760A1
SERIAL NO

17899305

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cho, Kwang-Ho Boise, US 5 2
Matsumoto, Miki Tokyo, JP 12 251

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