Importance

Loading Importance Indicators...

Abstract

A variable-length codeword encoder is disclosed which produces 8-bit output segments for storage in a buffer (23) for subsequent transmission over a transmission channel (24). The encoder includes two memory tables (15, 16), which produce in response to each input symbol to be encoded, a variable-length codeword and an a codeword length. An accumulator (31, 33) accumulates, modulo-8, the successive codeword lengths, producing a carry signal during any clock cycle in which eight or more bits codeword bits are accumulated. At each clock cycle, the variable-length codeword is input to the parallel inputs of a cross bar shift control circuit (30). This shift control circuit produces a 16-bit output in which the input word is embedded. The input word is shifted in the 16-bit output from the more significant bit positions to the less significant positions by a shift value determined from previous accumulated codeword lengths, with the shift value number of '0' bits being inserted in the more significant bit positions preceding the codeword. An OR circuit (38) combines the shifted variable-length codeword with previous variable-length codeword bits to form a concatenated sequence which is stored in upper and lower latches (53, 54). At any clock cycle, when the number of accumulated codeword bits is less than eight, the concatenated bits stored in the first and second latches are fed back to the OR circuit for combination at the next clock cycle with the next shifted variable-length codeword. When eight or more codeword bits are accumulated, the accumulator produces a carry signal and the 8-bit segment in the upper latch is outputted. The 8-bits in the lower latch are then shifted to the more significant bit positions of a concatenated sequence that is fed back to the OR circuit for combination with the next shifted variable-length codeword.

Loading the Abstract Image...

First Claim