Single-pass methods for generating test patterns for combinational circuits

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United States of America Patent

PATENT NO 6789222
APP PUB NO 20020091980A1
SERIAL NO

09754936

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method that finds all test vectors for all detectable single stuck-at faults in a combinational circuit during a single pass through the circuit sorts a netlist into circuit-level order, provides a library of fault-propagation and path-enabling rules for the circuit's logic elements, begins at the level of the primary inputs, and applies the rules, one logic element at a time, circuit-level-by-circuit-level until the entire circuit has been processed. The resulting fault-propagation functions for each output line define every combination of primary input signals that makes a fault detectable at that output line. In another embodiment, the method determines the highest circuit level at which each signal is used, and releases storage being used for previously computed fault-propagation functions and path-enabling functions for any signal having no further uses. The elimination of no longer needed stored information permits the method to handle larger circuits given finite resources.

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Patent Owner(s)

  • BUCKLEY, DELMAS R, JR

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Buckley, Jr Delmas Robert Palo Alto, CA 2 24

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