Method of manufacturing a floating gate with high gate coupling ratio
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United States of America Patent
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Oct 14, 1997
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N/A
app pub date -
Jan 7, 1997
filing date -
Jan 7, 1997
priority date (Note) -
Expired
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Abstract
The present invention is a method of manufacturing a floating gate with high gate coupling ratio for use in a EPROM and EEPROM. The gate coupling ratio is the ratio of the surface area of the inter-poly and the tunnel oxide. This invention utilizes a floating gate having a trench so as to increase the surface area of the inter-poly. Thus, a floating gate having high gate coupling ratio is achieved.
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