Apparatuses and methods for data management in a memory device
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United States of America Patent
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Feb 6, 2024
Grant Date -
Nov 25, 2021
app pub date -
May 21, 2020
filing date -
May 21, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
In some examples, a system may include a plurality of memory blocks, a first data bus coupled to the plurality of memory blocks in a memory device, a second data bus coupled to the plurality of memory blocks, a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus. The first memory block may be a cold data block least accessed among the plurality of memory blocks. The cold data transfer may be performed via the second data bus when a different memory block is being accessed via the first data bus concurrently. The second data bus may be a fuse bus in the memory device.
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