Compact and efficient CMOS inverter

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11302586
APP PUB NO 20210305105A1
SERIAL NO

16836590

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Abstract

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A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.

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Patent Owner(s)

  • INTEGRATED SILICON SOLUTION, (CAYMAN) INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beery, Dafna Palo Alto, US 43 100
Levi, Amitay Cupertino, US 73 710
Walker, Andrew J Mountain View, US 105 5599

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