Methods and semiconductor structures for latch-up suppression using a conductive region
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United States of America Patent
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Jun 1, 2010
Grant Date -
Oct 30, 2008
app pub date -
Jul 9, 2008
filing date -
Jan 26, 2006
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Expired
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Abstract
Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
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