Deep slit isolation with controlled void
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United States of America Patent
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-
Feb 11, 2003
Grant Date -
Nov 21, 2002
app pub date -
May 18, 2001
filing date -
May 18, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.
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