LDMOS using a combination of enhanced dielectric stress layer and dummy gates
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United States of America Patent
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Dec 18, 2012
Grant Date -
Feb 24, 2011
app pub date -
Nov 1, 2010
filing date -
Jul 17, 2006
priority date (Note) -
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Abstract
First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.
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