Inverting output driver circuit for reducing electron injection into the substrate

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO RE35764
SERIAL NO

08713757

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.CC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INCBOISE ID

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Casper, Stephen L Boise, ID 144 2779
Duesman, Kevin G Boise, ID 123 2397

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