Semiconductor device package with improved cooling
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United States of America Patent
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Aug 24, 2010
Grant Date -
N/A
app pub date -
Aug 31, 2006
filing date -
Oct 10, 2001
priority date (Note) -
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Abstract
A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.
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