Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

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United States of America Patent

PATENT NO RE41967
SERIAL NO

11337221

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Abstract

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A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

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Patent Owner(s)

Patent OwnerAddress
MIND FUSION LLC9407 NE VANCOUVER MALL DRIVE SUITE 104 #1253 VANCOUVER WA 98662-6191

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brannon, Sherwood 1098 SW. 21st Street 13 409
Cheung, Edmund 3530 Murdoch Dr. 7 239
Ishii, Takatoshi 771 Chopin Dr. 68 1498

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