Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme

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United States of America Patent

PATENT NO RE42600
SERIAL NO

11851242

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A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
POLYTECHNIC UNIVERSITYBROOKLYN, NY50

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chao, Hung-Hsiang Jonathan Holmdel, US 35 1241
Oki, Eiji Tokyo, JP 50 548
Rojas-Cessa, Roberto Brooklyn, US 20 150

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