ESD protection design with turn-on restraining method and structures
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United States of America Patent
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Feb 28, 2012
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N/A
app pub date -
Nov 9, 2006
filing date -
Feb 2, 2001
priority date (Note) -
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Abstract
The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.
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