Non-planar gate all-around device and method of fabrication thereof

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO RE50222
SERIAL NO

17410406

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Abstract

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A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

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Patent Owner(s)

  • SONY GROUP CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chau, Robert S Beaverton, US 516 19896
Kachian, Jessica S Portland, US 27 995
Kavaileros, Jack T Portland, US 1 0
Le, Van H Portland, US 275 3341
Pillarisetty, Ravi Portland, US 452 8118
Rachmady, Willy Beaverton, US 437 6352

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