System, method, and computer program product for property violation comprehension
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United States of America Patent
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Jan 8, 2019
Grant Date -
N/A
app pub date -
Feb 17, 2017
filing date -
Feb 17, 2017
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying at least one property violation associated with the electronic design. Embodiments may further include generating a sensitivity path from an input to the at least one property violation. Embodiments may also include analyzing the electronic design to identify one or more of a portion of the electronic design that caused the at least one property violation, a portion of the electronic design that did not cause the at least one property violation, and a portion of the electronic design that has not been analyzed. Embodiments may further include applying at least one of a depth analysis and a breadth analysis to the sensitivity path.
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