Signal processing circuit capable of avoiding cooperating memory chip from performance degradation
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United States of America Patent
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Dec 1, 2020
Grant Date -
Aug 6, 2020
app pub date -
Jan 13, 2020
filing date -
Jan 31, 2019
priority date (Note) -
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Abstract
A signal processing circuit includes: a printed circuit board (PCB) including a first surface layer, a second surface layer, a first reference layer, and a second reference layer, wherein the first and second surface layers are positioned on opposing side of the PCB while the first reference layer and the second reference layer are positioned between the first and second surface layers; a memory chip positioned on the first surface layer; a controller chip positioned on the second surface layer; a first set of signal lines arranged on the first surface layer and coupled with the memory chip, wherein all signal lines in the first set of signal lines does not cross each other; and a second set of signal lines arranged on the second surface layer and coupled with the controller chip, wherein all signal lines in the second set of signal lines does not cross each other.
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