Importance

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Abstract

Peripheral circuits each have a buffer connected to a common bus and output respective data transfer requests depending on the amount of data of the buffer. A data transfer circuit performs data transfer between a memory circuit and the buffer in response to the data transfer request. Each low-speed peripheral circuit of the peripheral circuits except a high-speed peripheral circuit having the largest transfer rate outputs the respective data transfer requests when a predetermined time has elapsed after the amount of data of the buffer became the amount sufficient to output the data transfer request. The high-speed peripheral circuit outputs a data transfer request when a time shorter than the predetermined time has elapsed after the amount of data of the buffer became the amount sufficient to output the data transfer request. Consequently, data that must be transferred within a predetermined period can be reliably transferred.

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First Claim