Sampling circuit and sampling method thereof

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United States of America Patent

APP PUB NO 20080136456A1
SERIAL NO

11953883

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Abstract

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A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to the sampling unit for delaying a sampling clock signal to output the first delayed signal; the inverter inverts the sampling clock signal to generate an inverted sampling clock signal; and the second delay chain is coupled to the inverter and the sampling unit for delaying the inverted sampling clock signal to output the second delayed signal.

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Patent Owner(s)

Patent OwnerAddress
REALTEK SEMICONDUCTOR CORP2 INNOVATION RD II SCIENCE PARK HSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Yi-Lin Taipei City, TW 68 231
Huang, Yi-Chih Hsin-Chu City, TW 10 14

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