Sampling circuit and sampling method thereof
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United States of America Patent
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Issued Date -
Jun 12, 2008
app pub date -
Dec 11, 2007
filing date -
Dec 12, 2006
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to the sampling unit for delaying a sampling clock signal to output the first delayed signal; the inverter inverts the sampling clock signal to generate an inverted sampling clock signal; and the second delay chain is coupled to the inverter and the sampling unit for delaying the inverted sampling clock signal to output the second delayed signal.
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