ALIGNMENT PROTECTION IN NON-VOLATILE MEMORY AND ARRAY

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United States of America Patent

SERIAL NO

11933377

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Abstract

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A memory device, a memory array and a method of arranging memory devices and arrays. The memory device includes a memory region including a plurality of memory cells, each memory cell with a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. The memory device includes a plurality of conductor lines. The memory includes a non-memory region having embedded logic including a plurality of transistors, each transistor for electrically coupling one of the conductor lines and each transistor including a transistor source, a transistor drain and a transistor gate.

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Patent Owner(s)

Patent OwnerAddress
MARVELL WORLD TRADE LTDST MICHAEL 14027

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wang, Chih-Hsin San Jose, CA 46 521

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