SEMICONDUCTOR PACKAGE WITH STACKED DIE ASSEMBLY

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United States of America Patent

APP PUB NO 20090261462A1
SERIAL NO

12103838

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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This application relates to semiconductor packages comprising stacked die assemblies. In some cases, the stacked dies comprise a first die containing gate driver IC that is stacked on a first surface of a second IC die. A second surface of the second IC die can be bumped for connection to one or more bump attach pads. The first die can be wire bonded to one or more bond attach pads. In some instances, the semiconductor packages include a leadframe clip that connects with the drain on the first die. In such instances, the gate driver IC of the first die can be stacked on a first surface of the leadframe clip and a second surface of the leadframe clip can be stacked on the first surface of the second IC die. The semiconductor packages can be molded and/or configured into a ball grid array (“BGA”) or a land grid array (“LGA”) configuration. Other embodiments are described.

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Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR COMPONENTS INDUSTRIES LLC5701 N PIMA ROAD SCOTTSDALE AS 85250

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gomez, Jocel Cebu , PH 3 32

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