METHOD AND SYSTEM FOR ANALYZING PERFORMANCE METRICS OF ARRAY TYPE CIRCUITS UNDER PROCESS VARIABILITY
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United States of America Patent
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Issued Date -
Sep 30, 2010
app pub date -
Mar 24, 2010
filing date -
Mar 25, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method is disclosed for analyzing a performance metric of an array type electronic circuit under process variability effects. The electronic circuit has an array with a plurality of array elements and an access path being a model of the array type electronic circuit. The model includes building blocks having all hardware to access one array element in the array. Each building block has at least one basic element. In one aspect, the method includes deriving statistics of the access path due to variations in the building blocks under process variability of the basic elements, and deriving statistics of the full array type electronic circuit by combining the results of the statistics of the access path under awareness of the array architecture.
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