Method for Designing Integrated Electronic Circuits Having Electrostatic Discharge Protection and Circuits Obtained Thereof
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United States of America Patent
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Issued Date -
Mar 3, 2011
app pub date -
Aug 26, 2010
filing date -
Aug 27, 2009
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Abandoned
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Abstract
A method for designing an integrated electronic circuit (1) having Electro Static Discharge (ESD) protection, the method comprising providing an integrated electronic circuit (1) having a predetermined performance during normal operation of the circuit, the integrated electronic circuit (1) comprising a power supply line (2) and at least one active device (4) protected by an ESD protection device (5), the active device (4) being powered from the power supply line (2), simulating an ESD event on the integrated electronic circuit (1) to determine if and where, during the ESD event, a parasitic ESD current path is created between the power supply line (2) and the at least one active device (4), and creating in thus determined parasitic ESD current path a circuit (6) to interrupt this parasitic ESD current path, at least during part of the ESD event.
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