Method for Designing Integrated Electronic Circuits Having Electrostatic Discharge Protection and Circuits Obtained Thereof

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United States of America Patent

APP PUB NO 20110051301A1
SERIAL NO

12869318

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Abstract

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A method for designing an integrated electronic circuit (1) having Electro Static Discharge (ESD) protection, the method comprising providing an integrated electronic circuit (1) having a predetermined performance during normal operation of the circuit, the integrated electronic circuit (1) comprising a power supply line (2) and at least one active device (4) protected by an ESD protection device (5), the active device (4) being powered from the power supply line (2), simulating an ESD event on the integrated electronic circuit (1) to determine if and where, during the ESD event, a parasitic ESD current path is created between the power supply line (2) and the at least one active device (4), and creating in thus determined parasitic ESD current path a circuit (6) to interrupt this parasitic ESD current path, at least during part of the ESD event.

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Patent Owner(s)

Patent OwnerAddress
IMECKAPELDREEF 75 LEUVEN 3001

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Linten, Dimitri Boortmeerbeek, BE 14 406
Thijs, Steven Willebroeck, BE 13 454

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