CIRCUITS INCORPORATING INTEGRATED PASSIVE DEVICES HAVING INDUCTANCES IN 3D CONFIGURATIONS AND STACKED WITH CORRESPONDING DIES
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United States of America Patent
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app pub date -
Aug 25, 2015
filing date -
Apr 2, 2014
priority date (Note) -
Abandoned
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Abstract
A circuit including: a die a first substrate and at least one active device; an integrated passive device including a first layer, a second substrate, a second layer and an inductance; and a third layer. The inductance includes vias and is an electrostatic discharge inductance. The vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars. The pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.
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