Importance

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Abstract

The plurality of flip-flops included in a logic circuit are grouped by the clock source, thereby judging a relatively large part of the clock skew. Namely, the relatively large clock skew generates between the scan flip-flop belonging to a certain group connected by the scan path and the scan flip-flop belonging to another group. Specifically, as the last scan flip-flop of each group is connected to the scan flip-flop belonging to another group, the scan flip-flop including the delay circuit is applied to the last scan flip-flop of each group, whereby it is possible to regulate the relatively large clock skew by use of the less number of basic cells by insertion of the buffer.

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First Claim