Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6849946
APP PUB NO 20020106886A1
SERIAL NO

09779123

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Abstract

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The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.

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Patent Owner(s)

Patent OwnerAddress
INVENSAS CORPORATION3025 ORCHARD PARKWAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Seams, Christopher A Pleasanton, CA 7 62
Sethuraman, Anantha R Fremont, CA 17 341

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