Computer system having an apportionable data bus and daisy chained memory chips

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United States of America Patent

PATENT NO 7844769
SERIAL NO

11459955

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Abstract

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A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.

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Patent Owner(s)

Patent OwnerAddress
LENOVO INTERNATIONAL LIMITED979 KING'S ROAD 23/F LINCOLN HOUSE TAIKOO PLACE QUARRY BAY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bartley, Gerald Keith Rochester, US 76 497
Becker, Darryl John Rochester, US 46 262
Borkenhagen, John Michael Rochester, US 57 1727
Dahlen, Paul Eric Rochester, US 51 289
Germann, Philip Raymond Oronoco, US 63 340
Maki, Andrew Benson Rochester, US 42 216
Maxson, Mark Owen Mantorville, US 51 262

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