Computer system having an apportionable data bus and daisy chained memory chips
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United States of America Patent
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Nov 30, 2010
Issued Date -
N/A
app pub date -
Jul 26, 2006
filing date -
Jul 26, 2006
priority date (Note) -
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Abstract
A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.
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