Integrated circuit die stacks with translationally compatible vias
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United States of America Patent
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Sep 4, 2012
Grant Date -
May 12, 2011
app pub date -
Nov 12, 2009
filing date -
Nov 12, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.
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