Receiver circuit

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United States of America Patent

PATENT NO 8472561
APP PUB NO 20120020399A1
SERIAL NO

13155485

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Abstract

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A receiver circuit includes: a first sampling circuit to sample input data in synchronization with a first edge of a sampling clock signal; a second sampling circuit to sample the input data in synchronization with a second edge of the sampling clock signal; a duty-cycle-distortion detection circuit to detect a duty-cycle-distortion amount indicating an error in a duty ratio of the sampling clock signal based on first data which is sampled by the first sampling circuit and second data which is sampled by the second sampling circuit; a correction circuit to correct the first data or the second data to generate first corrected data or second corrected data, respectively, based on the duty-cycle-distortion amount; and a clock data recovery circuit to select data out of the first corrected data and the second data and to recover the selected data.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Doi, Yoshiyasu Kawasaki, JP 23 162

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