Method for forming 3D-interconnect structures with airgaps
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United States of America Patent
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Feb 11, 2014
Grant Date -
Jan 19, 2012
app pub date -
Jul 14, 2011
filing date -
Jul 16, 2010
priority date (Note) -
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Abstract
Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.
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