Optimizing system throughput by automatically altering thread co-execution based on operating system directives

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United States of America Patent

PATENT NO 8898435
SERIAL NO

14093340

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Abstract

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A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.

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Patent OwnerAddress
LENOVO INTERNATIONAL LIMITED979 KING'S ROAD 23/F LINCOLN HOUSE TAIKOO PLACE QUARRY BAY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Merchant, Amit Bangalore, IN 17 716
Sarma, Dipankar Bangalore, IN 25 567
Srinivasan, Vaidyanathan Bangalore, IN 29 95

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