Method for providing a gate metal layer of a transistor device and associated transistor

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United States of America Patent

PATENT NO 9202695
APP PUB NO 20140332864A1
SERIAL NO

14271956

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Abstract

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A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the dummy gate electrode, and providing a final gate electrode layer in between the inner sidewalls of the set of spacers. Providing the final gate electrode layer further includes providing a diffusion layer that extends on top of the gate dielectric layer, on inner sidewalls of the spacers, and on a portion of a front surface of embedding layers for the dummy gate structure. Providing the final gate electrode also includes providing a metal on top of the diffusion layer, applying an anneal step, and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer. The present disclosure also relates to an associated transistor.

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Patent Owner(s)

Patent OwnerAddress
IMECKAPELDREEF 75 LEUVEN 3001

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Togo, Mitsuhiro Leuven, BE 24 132

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