Chip package and manufacturing method thereof
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United States of America Patent
Stats
-
Jan 17, 2017
Grant Date -
Oct 27, 2016
app pub date -
Apr 25, 2016
filing date -
Apr 27, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.
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