SYSTEM AND METHOD FOR PARALLEL DATA COMPRESSION AND DECOMPRESSION

World Intellectual Property Organization Patent

APP PUB NO WO-2000045516-A1
SERIAL NO

PCTUS0002355

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Abstract

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An integrated memory controller (IMC) including MemoryF/X Technology which includes data compression and decompression engines for improved performance. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF/X Technology encompasses multiple novel techniques such as: 1) parallel lossless compression/decompression; 2) selectable compression modes such as lossless, lossy or no compression; 3) priority compression mode; 4) data cache techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The parallel compression and decompression algorithm allows high-speed parallel compression and high-speed parallel decompression operation.

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Patent Owner(s)

Patent OwnerAddress
INTERACTIVE SILICON INCUSAUSTIN TX 78731

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Inventor(s)

Inventor Name Address
GEIGER PETER AUSTIN TX 78730
DYE THOMAS A AUSTIN TX 78731
ALVAREZ MANUEL J II AUSTIN TX 78717

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